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Circuits CMOS haute vitesse pour récepteurs optiques par Savoj, livre relié Jafar
66,28 $US
Environ91,27 $C
État :
Acceptable
Un livre présentant des traces d'usure apparentes. Sa couverture peut être endommagée, mais elle est globalement intacte. Sa reliure peut être légèrement endommagée, mais elle est globalement intacte. Il est possible que les marges portent des inscriptions ou que des passages aient été soulignés ou surlignés, mais il n'y a aucune page manquante et rien ne compromet la lisibilité ou la compréhension du texte.
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Expédition :
Sans frais USPS Media MailTM.
Lieu : San Diego, California, États-Unis
Livraison :
Livraison prévue entre le ven. 1 août et le lun. 4 août à 94104
Renvois :
Renvoi sous 30 jours. L'acheteur paie les frais de renvoi. Si vous utilisez une étiquette d'envoi eBay, son coût sera déduit du montant de votre remboursement.
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Magasinez en toute confiance
Le vendeur assume l'entière responsabilité de cette annonce.
Numéro de l'objet eBay :156739478214
Dernière mise à jour : juil. 30, 2025 18:07:50 HAEAfficher toutes les modificationsAfficher toutes les modifications
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Caractéristiques de l'objet
- État
- ISBN
- 9780792373889
À propos de ce produit
Product Identifiers
Publisher
Springer
ISBN-10
079237388X
ISBN-13
9780792373889
eBay Product ID (ePID)
9038416380
Product Key Features
Number of Pages
Xiv, 124 Pages
Publication Name
High-Speed Cmos Circuits for Optical Receivers
Language
English
Publication Year
2001
Subject
Electronics / Semiconductors, Electronics / Circuits / Integrated, Electronics / Circuits / General, Electronics / Optoelectronics, Electrical
Type
Textbook
Subject Area
Technology & Engineering
Format
Hardcover
Dimensions
Item Weight
30 Oz
Item Length
9.2 in
Item Width
6.1 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
2001-029732
Dewey Edition
21
Number of Volumes
1 vol.
Illustrated
Yes
Dewey Decimal
621.3827
Table Of Content
TIAs and Limiters.- Clock and Data Recovery Architectures.- A CMOS Interface for Detection of 1.2-Gb / s RZ Data.- A 10-Gb/s Linear Half-rate CMOS CDR Circuit.- A 10-Gb/s CMOS CDR Circuit with Wide Capture Range.- Conclusion.
Synopsis
With the exponential growth of the number of Internet nodes, the volume of the data transported on the backbone has increased with the same trend. The load of the global Internet backbone will soon increase to tens of terabits per second. This indicates that the backbone bandwidth requirements will increase by a factor of 50 to 100 every seven years. Transportation of such high volumes of data requires suitable media with low loss and high bandwidth. Among the available transmission media, optical fibers achieve the best performance in terms of loss and bandwidth. High-speed data can be transported over hundreds of kilometers of single-mode fiber without significant loss in signal integrity. These fibers progressively benefit from reduction of cost and improvement of perf- mance. Meanwhile, the electronic interfaces used in an optical network are not capable of exploiting the ultimate bandwidth of the fiber, limiting the throughput of the network. Different solutions at both the system and the circuit levels have been proposed to increase the data rate of the backbone. System-level solutions are based on the utilization of wave-division multiplexing (WDM), using different colors of light to transmit s- eral sequences simultaneously. In parallel with that, a great deal of effort has been put into increasing the operating rate of the electronic transceivers using highly-developed fabrication processes and novel c- cuit techniques.
LC Classification Number
TK7867-7867.5
Description de l'objet du vendeur
À propos de ce vendeur
Goodwill Industries San Diego Books
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